1. Field of the Invention
The invention relates to a circuit arrangement for adapting the bit rates of two signals, arrangement such comprising a justification decision circuit and also comprising, for example, an elastic store into which the data of a first signal are written in parallel in groups of n bits and read out again in signal are written in parallel in groups of n bits and read out again in parallel. A selection matrix for inserting justification bits is connected after the elastic store. The writing process is controlled by a write counter and the reading process by a read counter, and a subtractor that forms the difference between the counts is also connected after the elastic store.
2. Description of the Related Art
Such a circuit arrangement for adapting bit rates is described, for example, in the above-referenced German Patent Application No. DE 39 20 391 and corresponding U.S. application Ser. No. 540,996. Circuit arrangements of this type are necessary in data communication, for example, for plesiochronous multiplexers that combine plesiochronous signals. Two binary signals are termed plesiochronous when their bit rates are nominally equal, but may in fact deviate from the nominal value within a specific tolerance range. Before plesiochronous signals can be combined by a plesiochronous multiplexer, they all have to be brought to the same bit rate which (in so-called positive justification technology) is slightly higher than the bit rae the individual plesiochronous signals have. This difference between the bit rates is eliminated, inter alia, in that so-called justification bits are occasionally added to the signal having the higher bit rate. A circuit arrangement that carries out operations of this type is also termed a clock alignment circuit.
On the receive side of a transmission system a plesiochronous multiplexer can be connected after a corresponding bit rate adaptation circuit arrangement in order to remove the justification bits and bring the bit rate back to the original value. Justification decision circuits for circuit arrangements for adapting the bit rates of two binary signals, in which the signals are written into an elastic store in series and also read out again in series, are known (see, for example, DT 25 18 051 A, which corresponds to U.S. Pat. No. 4,002,844). If a circuit arrangement of this type is utilized for bit rates of the order of 140 Mbit/s and over, the arrangement--including the justification decision circuit--must be realised in ECL technology because CMOS circuits are not suited to operation at such high frequencies. However, in circuits employing ECL technology higher power losses occur than in comparable circuits in CMOS technology.